VLSI circuit technology is rapidly changing due to increases in VLSI circuit complexity, coupled with higher performance and smaller sizing requirements. Increasing importance of improving manufacturing testing techniques at all levels of VLSI integration is emerging due to newer technology, pressures for higher production yield requirements, and tighter time-to-market schedules. The focus of this invention lies in the art of testing computing devices during manufacture. As used hereinafter, a computing device may include a microprocessor, microcontroller, or any application specific integrated circuit (ASIC) which instantiates a processor core into it. A computing device may be used in a computing system, which may be used in a computer, automotive, communications, control, or other application.
During the manufacturing stage, electronic circuit testing generally occurs at each level of integration of the circuit via various testing techniques. Accordingly, testing generally occurs at the wafer level, package level, multi-chip module (MCM) level, board level, and system level. The goal of testing at each level is to detect as many defective circuits as possible before advancing to the next level of testing. Passing a defective circuit to the next level of integration increases product cost. Effective testing provides high fault coverage. Fault coverage may be defined as the ratio between the number of faults a test detects and the total number of faults in the circuit. A test having low fault coverage implies lower yield at the next level of integration, assuming that the test efficiency on the next test step is higher.
The testing techniques currently used in the industry are different at each level of testing. This is due in part to the difference in what is being tested and also what causes a fault at each testing level. At the wafer and package levels, a single component, which may be a microprocessor, microcontroller or ASIC, is being tested. A fault at the wafer or package level may, for example, be caused by a fabrication error such as particle causing shorts. In contrast, at the board and system levels, a system incorporating the component is being tested. A fault at these higher levels of testing may be due, for example, to a functional defect on a component or a solder defect.
At the wafer level, the testing goal is to separate good die from bad, before sawing and component packaging. A test with high fault coverage will ideally remove all fabrication errors. Wafer level testing techniques include parametric testing including current monitoring (IDDQ) testing, stuck-at testing, structural built-in self testing (BIST), internal scanpath testing, and at-speed parallel vector testing. Parametric testing tests if the input receivers and output drivers meet minimum electrical requirements such as threshold and bias voltage and leakage current specifications. The IDDQ testing technique places the CMOS logic of the circuit in a quiescent state and then measures the power supply current. If the current measured exceeds a preset threshold, the test has a detected a defect, and the die is rejected. Parametric testing is effective at detecting fabrication errors; however, it requires significant testing time to make the measurements. Stuck-at testing determines if internal inputs and outputs of logic gates are permanently stuck at a high or low logic level. Fabrication defects are modeled as stuck-at faults. Stuck logic levels adversely affect the logic function of the circuit. The effectiveness of the stuck-at testing technique is measured by the stuck-at fault coverage of the test, which may be defined as the ratio of the number of stuck-at faults tested to the number of actual stuck-at faults possible in the circuit. A high stuck-at fault coverage is desirable. The structural built-in selftest (BIST) technique at the wafer level uses automated hardware based tests contained inside the part which allow the circuit to test itself. The BIST may occur online during normal operation of the chip during an idle state, or offline when the circuit is placed in a special test mode. During wafer level testing, online BIST is employed and generally includes a hardware pseudo-random vector generator and signature analysis hardware. Although the BIST technique is an effective method of detecting stuck-at and delay type faults, it requires costly testing time and die space. Internal scanpath testing is a technique used to map a sequential circuit test generation problem into a combinational circuit test generation problem. Circuits must be pre-designed to include scanpath test hardware, which may include isolated or integrated scan or shadow registers. Automatic test pattern generation is used for achieving very high stuck-at test coverage for sequential circuits. Scanpath techniques also include at-speed functional tests which detect delay faults located in the latch-to-latch path being tested. Delay faults affect the timing of the circuit. A delay fault may be defined as a defect that causes the response of a gate or path in the circuit to be too slow, and therefore does not meet the required speed specifications. The component will perform incorrectly as the delay fault is propagated throughout the circuit. In the at-speed parallel vector functional testing technique, test vectors used in the simulation of the electronic circuit in the design phase are applied to the inputs of the electronic circuit device on a tester at the operating speed of the device. The outputs of the devices are then observed to determine if the operation of the device is correct. Although at-speed functional testing is effective in the detection of delay faults, this technique requires test equipment which operates at speeds slightly higher than the component target speed. IC testers capable of performing at-speed functional tests are very expensive and physical connection to the wafer becomes difficult if not impossible at frequencies required by current technology devices due to bandwidth limitations in the wafer probing connection to the silicon wafer.
Testing at the packaged integrated circuit (IC) level usually employs the same testing techniques as those performed at the wafer level. However, any performance limitations imposed by wafer prober bandwidth are removed, since at the packaged IC level one can create interconnects from the tester to the pins of the package that allow the rate of test vectors to be the same or higher than the component operating frequency. As a result, functional testing using at-speed parallel vectors becomes more viable at this level.
Testing at the board level is typically performed in two distinct steps, including assembly process testing and board functional testing. The assembly process test detects defects that occur during the manufacturing of the board such as solder shorts, opens, and reversed components. The board functional test verifies that the board performs according to its specifications. In computing system boards, the board functional test generally includes a microprogram based functional test and a software diagnostics test. A microprogram as used hereinafter is a sequence of elementary machine level instructions which correspond to computing device operations and whose execution is initiated by the introduction of a computing device instruction into an instruction register of the computing device. A microprogram based functional test as used hereinafter is a microprogram that is designed to test the functional operation of a computing device. The microprogram based functional testing technique allows a computing device to be tested by executing machine level instructions at the operating frequency of the computing device in an autonomous fashion. An example of a microprogram based functional test is the built-in selftest (BIST) that computer systems execute from a read-only memory (ROM) at power-up. The software diagnostic test portion of the board functional test require the system to be booted up and are run from the operating system level. Microprogram based functional tests provide an effective method for detecting the majority of functional defects at the board level due to their ability to be run at the operating speed of the circuit and their ability to perform operations that the computing device is designed to perform. However, isolation of the cause of the defect is difficult and requires the help of a skilled technician. Also, in a ROM-based BIST, the microprogram based functional test is developed and frozen by R&D in the design stage before the product is ramped to manufacturing. Since the coverage and isolation of a ROM-based BIST is static, it is very difficult to alter or add a new test, or control the testing such as looping on a failure. Without more flexible control of the microprogram based functional test, its fault coverage may be lower because it is usually not perfectly matched to the fault spectrum of the product.
The multi-chip module (MCM) level presents two testing alternatives. In one alternative, the MCM may be treated as a board. In this case, the board level assembly and functional testing technique may be applied to the MCM. Board level testing is difficult since critical components needed for BIST-type microprogram based functional testing such as an integrated boot ROM are missing. In another alternative, the MCM may be treated as an integrated circuit (IC). In this case the package level testing technique may be applied to the MCM. Package level testing at the MCM level is difficult due to its increased complexity.
System testing is performed once the final system is assembled. The system may contain multiple boards. System test is similar to board level functional test but relies more on operating system diagnostics in addition to the ROM based microprogram based functional test.
Each of the testing techniques discussed above for each testing level carry with them intendant problems. Circuit testing at the wafer level requires expensive testing time, die space, and engineering time in designing high fault coverage tests. In addition, if at-speed functional testing is performed, wafer level testing also incurs the high cost of at-speed functional test equipment and difficulty in applying the test due to the limited probing bandwidth of the testing equipment (approximately 150-200 MHz with current wafer probers). Packaged level circuit testing also suffers from the difficulty and expense of generating high fault coverage tests and the high costs of at-speed functional test equipment. Board level testing carries with it the intendant difficulties of diagnosing faults detected by a microprogram based BIST and its accompanying high cost of technician time in debug, along with difficulties in altering or improving BIST fault coverage. Testing at the MCM level suffers from increased circuit complexity and the difficulty in pinpointing a defective component which may have escaped detection at a lower testing level. A need exists to solve the above problems.
A related area in computing system development technology is the need for computer device emulation by the developers of final product computing systems. A recent innovation is the implementation of a debug port for emulation and internal emulation debug hardware within the computing device itself. Emulation as used hereinafter includes the ability to control execution and to read and write registers, memory and I/O of a computing device. Access to the emulation debug hardware is provided through an emulation debug port of the computing device. Most new microprocessors and microcontrollers now include an emulation debug port as a standard feature. The purpose of the emulation debug port is to assist system developers in the emulation debug process used when they are developing the system firmware around the computing device. In the recent past system developers used system emulators and emulation pods to debug and develop system firmware, but with the complexity and difficulty in physical access to modern VLSIs, the industry has moved to implementing the emulation hardware inside the computing device and making them accessible via the debug port. It would be desirable to provide a system and method to take advantage of internal emulation debug hardware of a computing device when testing the computing device or system incorporating the computing device during manufacturing.